1. Field of the Invention
The invention relates generally to lithography methods and lithography structures for fabricating dual damascene structures within microelectronic structures. More particularly, the invention relates to enhanced performance lithography methods and lithography structures for fabricating dual damascene structures within microelectronic structures.
2. Description of the Related Art
Microelectronic structures, and in particular semiconductor structures, are fabricated using lithographic methods. Lithographic methods typically include the use of successive resist layers that are latently imaged and subsequently developed and patterned over a substrate, such as but not limited to a semiconductor substrate, for purposes of fabricating any of several structures within the substrate. Particular structures that may be fabricated within or over a semiconductor substrate while using a patterned resist layer include selectively deposited structures and selectively etched structures, as well as selectively ion implanted structures.
A particularly desirable microelectronic structure that is commonly lithographically fabricated within the context of semiconductor structures is a dual damascene structure. Dual damascene structures are metallization structures that include, within a dielectric layer: (1) a lower lying via aperture; that is contiguous with and overlapped by (2) an upper lying trench aperture. At least a portion of an underlying conductor layer is typically exposed at the bottom of the lower lying via aperture. Typically formed within a dual damascene aperture is: (1) a via within the via aperture (i.e., where the via contacts the underlying conductor layer); that is contiguous with (2) an interconnect within the trench aperture. When forming the dual damascene aperture in general, various methods are known where either a via aperture may be formed first, or alternatively a trench aperture may be formed first.
While dual damascene apertures and the corresponding vias and contiguous interconnects which are located and formed therein certainly provide process efficiency when fabricating microelectronic structures, dual damascene structures are in general not entirely without problems. In particular as microelectronic technology advances, and microelectronic structure and device dimensions decrease, dual damascene apertures also often become more difficult to efficiently fabricate with decreasingly scaled dimensions. In particular, it is increasingly difficult to assure level to level overlay that provides proper connection to dual damascene structures within microelectronic structures. In addition, it is also becoming more difficult to assure proper via aperture and trench aperture alignment within a given particular dual damascene aperture which comprises a dual damascene structure.
Various methods for fabricating dual damascene structures within microelectronic structures are known in the microelectronic fabrication art.
For example, Yang et al., in U.S. Pat. No. 7,056,821, teaches a particular method for fabricating a dual damascene structure within a dielectric layer to provide for inhibited atmospheric exposure of an underlying conductor layer to which a via connection is made within the dual damascene structure. The particular method is a trench first method that uses an etch stop layer located upon the underlying conductor layer, where the etch stop layer is not etched to expose the underlying conductor layer until after forming the trench and the via within the dielectric layer.
In addition, Uglow et al., in U.S. Pat. No. 7,060,605, teaches another particular method for fabricating a dual damascene structure within a dielectric layer with enhanced process efficiency and performance. The particular method uses in-part a low dielectric constant dielectric material within a portion of the dielectric layer within which is formed the dual damascene aperture.
Dual damascene apertures and dual damascene structures are likely to continue to be prevalent as microelectronic technology, and in particular semiconductor technology, advances. Thus, desirable are dual damascene apertures and dual damascene structures with continuing scaled dimensions, as well as methods for fabricating those dual damascene apertures and dual damascene structures with continuing scaled dimensions.